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B003664 - PRINCIPLE OF ELECTRONICS
Main information
Teaching Language
Course Content
Suggested readings
Learning Objectives
Prerequisites
Teaching Methods
Type of Assessment
Course program
Academic Year 2015-16
Coorte 2014 - 3-years First Cycle Degree (DM 270/04) in Electronics and Telecommunications Engineering
Course year
Second year - First Semester
Belonging Department
Information Engineering (DINFO)
Course Type
Single education field course
Scientific Area
ING-INF/01 - ELECTRONIC ENGINEERING
Credits
6
Teaching Hours
54
Teaching Term
21/09/2015 ⇒ 18/12/2015
Attendance required
No
Type of Evaluation
Final Grade
Course Content
show
Course program
show
Lectureship
Mutuality
Course teached as:
B013629 - ELETTRONICA
3-years First Cycle Degree (DM 270/04) in COMPUTER ENGINEERING
B013629 - ELETTRONICA
3-years First Cycle Degree (DM 270/04) in COMPUTER ENGINEERING
Teaching Language
Italian
Course Content
Semiconductors; pn junction; photodiodes and LED; FET; BJT; linear amplifiers; logics and memory
Suggested readings (Search our library's catalogue)
M. Pieraccini "Fondamenti di Elettronica" 2014, Pearson
Learning Objectives
.
Prerequisites
Basic Physics (electric charge, current, electrostatics, electrodynamics)
Theory of Circuits (Analysis of linear circuits)
Theory of Circuits (Analysis of linear circuits)
Teaching Methods
1) lessons on the blackboard (no slides)
2) exercices in classroom
2) exercices in classroom
Type of Assessment
Rules of examination
General Electronics (6 credits) and Electronics (9 credits)
1) During the course, two written partial tests will be carried out, they will consist of exercises and multiple-choice questions. Students are allowed to consult a personal note of a single A4 page with characters larger than 8p. The dates of tests are the same for both courses.
2) Students who have decided do not to take the partial test, or even they have obtained at one of the two a mark lesser than 15, at the end of the course they can take a complete written test (exercises and multiple choice questions). Any failure in a written test does not affect participation in the next written test. The written test can be repeated to improve the mark. It is worth the highest mark (although if it is not the most recent). The complete test in the calculation of the final mark is weighted as two partial tests.
3) The oral test consists of a single question of theory. The student can ask for a second question . The date of oral test is fixed in agreement with the teacher (not necessarily in conjunction with an appeal). To access the oral test, the students must have obtained almost 15 in the written test. The students cannot repeat the oral test to improve the vote, if the final mark is greater than 18.
4) The final mark is the weighted average between written test (weight = 2) and oral test.
General Electronics (6 credits) and Electronics (9 credits)
1) During the course, two written partial tests will be carried out, they will consist of exercises and multiple-choice questions. Students are allowed to consult a personal note of a single A4 page with characters larger than 8p. The dates of tests are the same for both courses.
2) Students who have decided do not to take the partial test, or even they have obtained at one of the two a mark lesser than 15, at the end of the course they can take a complete written test (exercises and multiple choice questions). Any failure in a written test does not affect participation in the next written test. The written test can be repeated to improve the mark. It is worth the highest mark (although if it is not the most recent). The complete test in the calculation of the final mark is weighted as two partial tests.
3) The oral test consists of a single question of theory. The student can ask for a second question . The date of oral test is fixed in agreement with the teacher (not necessarily in conjunction with an appeal). To access the oral test, the students must have obtained almost 15 in the written test. The students cannot repeat the oral test to improve the vote, if the final mark is greater than 18.
4) The final mark is the weighted average between written test (weight = 2) and oral test.
Course program
1) PHYSICS OF SEMICONDUCTORS
Ohm's law. Insulators and conductors. Semiconductors. Electrons in semiconductors. Gaps. Tunnel effect. Wave-particle duality. Intrinsic silicon. Silicon doped with n-type impurities. Silicon doped with p-type impurities. Law of mass action. Diffusion current. Built-in potential. Fermi energy. Silicon technology. Exercises.
2) THE PN JUNCTION
Realisation of a a pn junction. Diode. Depletion region. Band model. Metal-semiconductor junction. The pn diode complete. Principle of operation of a diode. Carrier concentration at the edge of the depletion region. Charge injection and recombination. Derivation of the characteristic of the diode. Current diffusion and drift in the diode. Limits of the ideal diode. Traps in the band gap. The Zener diode. Exercises.
3) PHOTODIODES and LED (only for 9 credits course)
Light-semiconductor interaction. The photodiode. Sensor matrix camera. Conversion efficiency of a photovoltaic cell. Semiconductors direct and indirect. LED. Exercises.
4) THE EFFECT TRANSISTOR FIELD
The transistor. Types of field effect transistor. The MOS capacitor. Calculation of the threshold voltage. N-channel enrichment MOSFET. N-channel MOSFET for large voltages. Cut-off of the MOSFET. Channel modulation. Physical realization of the MOSFET. N-channel enrichment MOSFET with resistive load. MOSFET as a voltage amplifier. Polarization of the n-channel Enrichment MOSFET. Bias network with source resistance. Bias with current generator. Current mirror. Bias network with gate resistance. MOSFET in saturation as active load. Depletion MOSFET. Bias network of a depletion MOSFET. Depletion MOSFET as active load. Enrichment P-channel MOSFET. 4-terminals MOSFET. Body effect. JFET. Derivation of the characteristic of the JFET. Exercises.
5) THE BIPOLAR TRANSISTOR
The BJT. Physical implementation of the BJT. Operation regions. Forward active region. Reverse active region. Interdiction. Saturation. Output characteristic of the BJT. Early effect. The BJT PNP. The BJT as switch. The BJT as a voltage amplifier. Polarization of the BJT. 4-resistors bias network. Polarization of the BJT by current generator. Current mirror. BJT vs. FET. Exercises.
FIRST WRITTEN PARTIAL TEST
6) LOGIC FAMILIES AND MEMORIES (only for 9 credits course)
Basic architecture of digital systems. Logic families. Ideal switch and resistor. Complementary ideal switches. CMOS logic. Classification of memories. Static RAM. Dynamic RAM. FLASH. Exercises.
7) LINEAR AMPLIFIERS
Linear amplifiers. Superposition Principle and non-linearity. Linearized model of the FET with 3 terminals. Linearized model of the FET with 4-terminal. The three configurations of the MOSFET. Linearized model of the BJT. Resistances seen from the three terminals of the BJT. The three configurations of the BJT. Analysis and design. Analysis of a voltage amplifier in single MOSFET in configuration CS. Design of voltage amplifier with a single MOSFET in CS configuration. Design of a voltage buffer with a single MOSFET in CD configuration. Exercises.
8) FREQUENCY RESPONSE OF LINEAR AMPLIFIERS
Frequency response of amplifiers. Frequency response of linear networks. Frequency response of a CS amplifier at low frequencies. General rule for the estimation of the cut-off frequency lower. Amplifiers at high frequencies. Capacity between gate and source in the MOSFET in saturation. Response of a CS amplifier at high frequency. Model of the MOSFET at high frequency. Parasitic capacitances of the BJT. Model of the BJT high frequency. General rule for estimating the higher cutoff frequency. Cascode. Exercises.
9) DESIGN OF ELECTRONIC CIRCUITS BY SOFTWARE CAD (computer-aided design)
Circuit pattern. Simulations circuit. Exercises.
SECOND PARTIAL WRITTEN TEST AND TOTAL WRITTEN TEST (for those who did not take the first partial test or has obtained an insufficient score at the first partial test)
Ohm's law. Insulators and conductors. Semiconductors. Electrons in semiconductors. Gaps. Tunnel effect. Wave-particle duality. Intrinsic silicon. Silicon doped with n-type impurities. Silicon doped with p-type impurities. Law of mass action. Diffusion current. Built-in potential. Fermi energy. Silicon technology. Exercises.
2) THE PN JUNCTION
Realisation of a a pn junction. Diode. Depletion region. Band model. Metal-semiconductor junction. The pn diode complete. Principle of operation of a diode. Carrier concentration at the edge of the depletion region. Charge injection and recombination. Derivation of the characteristic of the diode. Current diffusion and drift in the diode. Limits of the ideal diode. Traps in the band gap. The Zener diode. Exercises.
3) PHOTODIODES and LED (only for 9 credits course)
Light-semiconductor interaction. The photodiode. Sensor matrix camera. Conversion efficiency of a photovoltaic cell. Semiconductors direct and indirect. LED. Exercises.
4) THE EFFECT TRANSISTOR FIELD
The transistor. Types of field effect transistor. The MOS capacitor. Calculation of the threshold voltage. N-channel enrichment MOSFET. N-channel MOSFET for large voltages. Cut-off of the MOSFET. Channel modulation. Physical realization of the MOSFET. N-channel enrichment MOSFET with resistive load. MOSFET as a voltage amplifier. Polarization of the n-channel Enrichment MOSFET. Bias network with source resistance. Bias with current generator. Current mirror. Bias network with gate resistance. MOSFET in saturation as active load. Depletion MOSFET. Bias network of a depletion MOSFET. Depletion MOSFET as active load. Enrichment P-channel MOSFET. 4-terminals MOSFET. Body effect. JFET. Derivation of the characteristic of the JFET. Exercises.
5) THE BIPOLAR TRANSISTOR
The BJT. Physical implementation of the BJT. Operation regions. Forward active region. Reverse active region. Interdiction. Saturation. Output characteristic of the BJT. Early effect. The BJT PNP. The BJT as switch. The BJT as a voltage amplifier. Polarization of the BJT. 4-resistors bias network. Polarization of the BJT by current generator. Current mirror. BJT vs. FET. Exercises.
FIRST WRITTEN PARTIAL TEST
6) LOGIC FAMILIES AND MEMORIES (only for 9 credits course)
Basic architecture of digital systems. Logic families. Ideal switch and resistor. Complementary ideal switches. CMOS logic. Classification of memories. Static RAM. Dynamic RAM. FLASH. Exercises.
7) LINEAR AMPLIFIERS
Linear amplifiers. Superposition Principle and non-linearity. Linearized model of the FET with 3 terminals. Linearized model of the FET with 4-terminal. The three configurations of the MOSFET. Linearized model of the BJT. Resistances seen from the three terminals of the BJT. The three configurations of the BJT. Analysis and design. Analysis of a voltage amplifier in single MOSFET in configuration CS. Design of voltage amplifier with a single MOSFET in CS configuration. Design of a voltage buffer with a single MOSFET in CD configuration. Exercises.
8) FREQUENCY RESPONSE OF LINEAR AMPLIFIERS
Frequency response of amplifiers. Frequency response of linear networks. Frequency response of a CS amplifier at low frequencies. General rule for the estimation of the cut-off frequency lower. Amplifiers at high frequencies. Capacity between gate and source in the MOSFET in saturation. Response of a CS amplifier at high frequency. Model of the MOSFET at high frequency. Parasitic capacitances of the BJT. Model of the BJT high frequency. General rule for estimating the higher cutoff frequency. Cascode. Exercises.
9) DESIGN OF ELECTRONIC CIRCUITS BY SOFTWARE CAD (computer-aided design)
Circuit pattern. Simulations circuit. Exercises.
SECOND PARTIAL WRITTEN TEST AND TOTAL WRITTEN TEST (for those who did not take the first partial test or has obtained an insufficient score at the first partial test)